NEC V850ES/F 3-L Series User Manual page 551

32-bit single-chip microcontroller
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CAN Controller (CAN)
(3)
Figure 18-20
Synchronizing data bit
• The receiving node establishes synchronization by a level change on the
bus because it does not have a sync signal.
• The transmitting node transmits data in synchronization with the bit timing of
the transmitting node.
(a) Hardware synchronization
This synchronization is established when the receiving node detects the start
of frame in the interframe space.
• When a falling edge is detected on the bus, that TQ means the sync
segment and the next segment is the prop segment. In this case,
synchronization is established regardless of SJW.
Interframe space
CAN bus
Bit timing
Adjusting synchronization of data bit
(b) Resynchronization
Synchronization is established again if a level change is detected on the bus
during reception (only if a recessive level was sampled previously).
• The phase error of the edge is given by the relative position of the detected
edge and sync segment.
<Sign of phase error>
0:
If the edge is within the sync segment
Positive:
If the edge is before the sample point (phase error)
Negative:
If the edge is after the sample point (phase error)
If phase error is positive: Phase segment 1 is lengthened by specified
SJW.
If phase error is negative: Phase segment 2 is shortened by specified
SJW.
• The sample point of the data of the receiving node moves relatively due to
the "discrepancy" in the baud rate between the transmitting node and
receiving node.
User's Manual U18743EE1V2UM00
Start of frame
Sync
Prop
Phase
segment
segment
segment 1
Chapter 18
Phase
segment 2
551

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