Power Save Modes Overview - NEC V850ES/F 3-L Series User Manual

Chapter 4

4.1.3 Power save modes overview

HALT mode
IDLE1 mode
IDLE2 mode
STOP
Subclock operation
Sub-IDLE mode
164
The power consumption of the system can be effectively reduced by using the
stand-by modes and selecting the appropriate mode for the application. The
available stand-by modes are listed below.
The following explanations provide a general overview. For details, please refer
to "Power save modes description" on page 196 and the register descriptions.
Mode in which only the operating clock of the CPU (f
clocks remain active.
This mode is entered by executing the HALT instruction. All other power save
modes are entered by setting registers.
This mode allows quick recovery to the normal operating mode, because it is
not necessary to wait for oscillators to be stable or the PLL to be locked.
Mode in which all the internal operations of the chip except the oscillators, PLL
and flash memory are stopped. The PLL holds the previous operating status.
This mode allows quick return to the normal operating mode in response to a
release signal, because it is not necessary to wait for oscillators to settle or the
PLL to lock.
Mode in which all the internal operations of the chip except the oscillators are
stopped.
Mode in which all the internal operations of the chip except the Sub oscillator
are stopped.
Mode in which the subclock is used as the CPU system clock f
source can be the SubOSC (f
selection is made by the SUBCLK bit of the option byte 007B
A mode that can be entered during subclock operation. All the internal
operations of the chip except the oscillator, PLL and flash memory are
stopped. The PLL holds the previous operating status.
User's Manual U18743EE1V2UM00
) or the 240 KHz internal oscillator (f
XT
Clock Generator
) is stopped. All other
CPU
. Subclock
VBCLK
). The
RL
.
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