NEC V850ES/F 3-L Series User Manual page 210

32-bit single-chip microcontroller
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Chapter 4
Leaving sub-IDLE
mode
Note
Table 4-35
Releasing Source
Non-maskable interrupt
request signal
Maskable interrupt
request signal
210
The sub-IDLE mode is released by a non-maskable interrupt request signal
(NMI pin input or INTWDT2 signal), unmasked external interrupt request
signal, unmasked internal interrupt request of a peripheral function that can
operate in the sub-IDLE mode, or reset signal.
The PLL returns to the operation status before the sub-IDLE mode was set.
When the sub-IDLE mode is released by an interrupt request signal, the
subclock operation mode is restored. When the sub-IDLE mode is released by
RESET, the normal operation mode is restored.
1.
Interrupt request signals that are disabled by the NMI1M, NMI0M, and
INTM bits of the PSC register are invalid and do not release the sub-IDLE
mode.
2.
When digital noise elimination is enabled for INTP3, the power save mode
cannot be released using INTP3 pin. For details, refer to "Pin Functions" on
page 31.
(a) Release by non-maskable interrupt request or unmasked maskable
interrupt request
The sub-IDLE mode is released by a non-maskable interrupt signal or an
unmasked maskable interrupt request signal, regardless of the priority of the
interrupt request signal.
If the sub-IDLE mode is set in an interrupt routine, however, the operation is
performed as follows:
• Interrupt request signals that are set (disabled) by the NMI1M, NMI0M, and
INTM bits of the PSC register are invalid and do not release the sub-IDLE
mode.
• If an interrupt request signal having a priority lower than that of the interrupt
request currently being serviced is generated, the sub-IDLE mode is
released, but the interrupt request with the lower priority is not
acknowledged. The interrupt request signal itself is held.
• If an interrupt request signal (including a non-maskable interrupt request
signal) having a priority higher than that of the interrupt request currently
being serviced is generated, the sub-IDLE mode is released, and this
interrupt request signal is acknowledged.
Operation after sub-IDLE mode is released by interrupt request signal
Interrupt Enabled (EI) Status
Execution branches to the handler address.
Execution branches to the handler address,
or the next instruction is executed.
(b) Releasing by RESET input
The operation is the same as the normal reset operation.
User's Manual U18743EE1V2UM00
Clock Generator
Interrupt Disabled (DI) Status
The next instruction is executed.

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