NEC V850ES/F 3-L Series User Manual page 420

Chapter 15
(2)
Caution
After reset: 00H
7
UDnCTL1 0
R/W R
SELCNTm
a
register
ISELn UDnCKS3
0
0
1
X 0
X 0
X 0
X 0
X 0
X 0
X 0
X 1
X 1
X 1
X 1
a)
For detailed information concerning the SELCNTm register refer to
b)
f has hte same frequency as f
XP2
c)
ASCKD0 is an external clock only for UARTD0. For UARTD1-5 the setting is prohibited.
Note
420
UDnCTL1 - UARTDn control register 1
The UDnCTL1 register is an 8-bit register that selects the UARTDn base clock.
This register can be read or written in 8-bit units.
Reset input clears this register to 00H.
Clear the UDnCTL0.UDnPWR bit to 0 before rewriting the UDnCTL1 register.
Address:
6 5
0 0
R R
UDnCTL1 register
UDnCKS2 UDnCKS1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
Other than above
, but does not stop in IDLE1 mode.
XP1
PRSI can be set by the option bytes:
Refer to "Flash Memory" on page 259 for details.
User's Manual U18743EE1V2UM00
Asynchronous Serial Interface (UARTD)
UD0CTL1: FFFFFA01, UD1CTL1: FFFFFA11
UD2CTL1: FFFFFA21
4 3
0 UDnCKS3 UDnCKS2 UDnCKS1 UDnCKS0
R R/W
UDnCKS0 Input
f
0
f
XP2
1 f
XP1
0 f
XP1
1 f
XP1
0 f
XP1
1 f
XP1
0 f
XP1
1 f
XP1
0 f
XP1
1 f
XP1
0 f
XP1
1
"Clock Generator" on page 179
2 1
R/W R/W
Input clock (f )
CLK
PRSI = 0
f
XP1 XX
b
f
XX
/2 f /2
XX
/4 f /4
XX
/8 f /8
XX
/16 f /16
XX
/32 f /32
XX
64 f /64
XX
/128 f /128
XX
/256 f /256
XX
/512 f /512
XX
/1024 f /1024
XX
– ASCKA0
– Setting prohibited
0
R/W
PRSI = 1
f
/2
XX
f
/2
XX
f
/4
XX
f
/8
XX
f
/16
XX
f
/32
XX
f
/64
XX
f
/128
XX
f
/256
XX
f
/512
XX
f
/1024
XX
f
/2048
XX
c
.