NEC V850ES/F 3-L Series User Manual page 205

Clock Generator
Table 4-31
Timer/counter TAA0 -TAA4 Stops operation
TMM0
Watch Timer (WT)
Watchdog Timer (WDT2)
AD convertor
Serial Interface UARTD0-2
CSIB0-1
IIC00
CAN Controller (CAN0)
Interrupt Controller
Key interrupting function
Clock Monitor
Power-On-Clear circuit
Low-Voltage Detector
Voltage Regulator
Internal data
Note
Leaving STOP mode
Note
Controller status in STOP mode (2/2)
Without Subclock
Operable if fBRG (clock of dividing
frequency of Prescaler3) is selected as
count clock.
Stops operation
Operable if f is selected as count clock.
RL
Stops operation
UARTD0: Operable if ASCKD0 is selected input clock
UARTD1-2: Operation stops.
Operable, if SCKBn is selected as input clock.
Stops operation
Stops operation
Stops operation (But it is possible to leave STOP Mode)
Operable
Stops operation
Operable
Operable
Operation continuous
The CPU registers, states, data and all other internal data such as the contents of
the internal RAM are retained as they were before STOP mode was set
1. If the STOP mode is set while the A/D Converter is operating, the A/D
Converter is automatically stopped and starts operating again after the
STOP mode is released. However, in that case, the A/D conversion results
up to the second conversion after the STOP mode is released are invalid
(the third or later conversion results are valid). All the A/D conversion
results before the STOP mode was set are invalid.
2. The power consumption in STOP mode is the same, no matter whether the
A/D Converter was operating or stopped before the STOP mode was set.
The STOP mode is released by a non-maskable interrupt request signal (NMI
pin input or INTWDT2 signal), unmasked external interrupt request signal,
unmasked internal interrupt request signal of a peripheral function that can
operate in the STOP mode, or reset signal.
When the STOP mode has been released, the normal operation mode is
restored.
1. Interrupt request signals that are disabled by the NMI1M, NMI0M, and
INTM bits of the PSC register are invalid and do not release the STOP
mode.
2. When digital noise elimination is enabled for INTP3, the power save mode
cannot be released using INTP3 pin. For details, refer to "Pin Functions" on
page 31.
(a) Release by non-maskable interrupt request or unmasked maskable
interrupt request
User's Manual U18743EE1V2UM00
Working condition
With Subclock
Operable if f
RL
selected as count clock.
Operable if f
XT
clock.
Chapter 4
/8, INTWT or f is
XT
is selected as count
205