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Asynchronous Serial Interface (UARTD)
15.3 UARTD Registers
(1)
UDnCTL0 - UARTDn control register 0
The UDnCTL0 register is an 8-bit register that controls the UARTDn serial
transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset input sets this register to 10H.
7
UDnCTL0
UDnPWR
UDnTX E UDnRX E UDnDI R
UDnPWR
0
Disable UARTDn operation (UARTDn reset asynchronously)
1
Enable UARTDn operation
The UARTDn operation is controlled by the UDnPWR bit. The TXDDn pin output
is fixed to high level by clearing the UDnPWR bit to 0 (fixed to low level if
UDnOPT0.UDnTDL bit = 1).
UDnTXE
0
Disable transmission operation
1
Enable transmission operation
• To start transmission, set the UDnPWR bit to 1 and then set the UDnTXE bit to 1.
To stop transmission clear the UDnTXE bit to 0 and then UDnPWR bit to 0.
• To initialize the transmission unit, clear the UDnTXE bit to 0, wait for two cycles of
the base clock, and then set the UDnTXE bit to 1 again.
UDnRXE
0
Disable reception operation
1
Enable reception operation
• To enable reception, set the UDnPWR bit to 1 and then set the UDnRXE bit to 1.
•
To stop reception, clear the UDnRXE bit to 0 and then UDnPWR bit to 0.
•
To initialize the reception unit, clear the UDnRXE bit to 0, wait for two periods of
the base clock, and then set the UDnRXE bit to 1 again.
The reception is enabled after the UDnRXE bit is set to 1 and two cycles of base
clock have passed.
The rising edge detection of the RXDD pin is enabled after the UDnRXE bit is set to
1 and four cycles of the base clock have passed.
User's Manual U18743EE1V2UM00
UD2CTL0 FFFFFA20H, UD3CTL0 FFFFFA30H,
UD4CTL0 FFFFFA40H, UD5CTL0 FFFFFA50H
UD6CTL0 FFFFFA60H, UD7CTL0 FFFFFA70H
6
5
4
UARTDn operation control
Transmission operation enable
Reception operation enable
Chapter 15
3
2
1
UDnPS 1 UDnPS 0
UDnC L
0
UDnSL
395
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