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Chapter 4
Oscillation
waveform
Main clock
IDLE mode
status
Interrupt
request
Figure 4-7
(4)
Entering STOP
mode
STOP mode status
Table 4-31
MainOSC (f
)
X
SubOSC (f
)
XT
240 KHz internal oscillator (f
8 MHz internal oscillator (f
PLL (f
)
PLLO
CPU
Port function
204
ROM circuit stops.
IDLE2 mode timing
STOP mode
In the STOP mode, the subclock oscillator continues operating, but the main
clock oscillator stops operating. Moreover, clock supply to the CPU and the
other on-chip peripheral functions is stopped.
As a result, program execution is stopped, and the contents of the internal
RAM before the STOP mode was set are retained. Not only the CPU but also
the other on-chip peripheral functions stop operating. However, the on-chip
peripheral functions that can operate on the subclock or external clock
continue operating.
The STOP mode can reduce current consumption more than the IDLE2 mode
because the operation of the main clock oscillator is stopped. When the
subclock oscillator, internal oscillator, and external clock are not used, the
current consumption can be substantially reduced with only a leakage current
flowing.
The STOP mode is set when the PSM1 and PSM0 bits of the PSMR register
are set to "01" or "11", and the STP bit of the PSC register is set to 1 in the
normal operation mode.
Insert five or more NOP instructions after the store instruction that manipulates
the PSC register to set the STOP mode.
The following table shows the operation status in the STOP mode.
Controller status in STOP mode (1/2)
Without Subclock
Stops operation
-
) Oscillation enabled
RL
)
Stops operation
RH
Stops operation
Stops operation
Holds status before STOP mode is set
User's Manual U18743EE1V2UM00
Counting of setup time
Working condition
Oscillation enabled
Clock Generator
With Subclock
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