NEC V850ES/F 3-L Series User Manual page 235

32-bit single-chip microcontroller
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Interrupt Controller (INTC)
Note
Main routine
EI
Interrupt request i
(level 2)
Interrupt request l
(level 2)
Interrupt request o
(level 3)
Interrupt request s
(level 1)
Figure 5-8
1.
<a> to <u> in the figure are the temporary names of interrupt requests
shown for the sake of explanation.
2.
The default priority in the figure indicates the relative priority between two
interrupt requests.
Processing of i
EI
Interrupt
request j
(level 3)
Interrupt request k
(level 1)
Processing of j
Processing of l
Interrupt
request m
(level 3)
Interrupt request n
(level 1)
Processing of n
Processing of m
Processing of o
EI
EI
Interrupt
Interrupt
request p
request q
(level 2)
(level 1)
Processing of s
Interrupt
request t
Note 1
(level 2)
Interrupt request u
Note 2
(level 2)
Processing of u
Processing of t
Example of processing in which another interrupt request is issued
while an interrupt is being processed (2/2)
User's Manual U18743EE1V2UM00
Processing of k
Interrupt request j is held pending because its
priority is lower than that of i.
k that occurs after j is acknowledged because it
has the higher priority.
Interrupt requests m and n are held pending
because processing of l is performed in the
interrupt disabled status.
Pending interrupt requests are acknowledged after
processing of interrupt request l.
At this time, interrupt requests n is acknowledged
first even though m has occurred first because the
priority of n is higher than that of m.
Processing of p
Processing of q
EI
Interrupt
request r
(level 0)
If levels 3 to 0 are acknowledged
Pending interrupt requests t and u are
acknowledged after processing of s.
Because the priorities of t and u are the same, u is
acknowledged first because it has the higher
default priority, regardless of the order in which the
interrupt requests have been generated.
Processing of r
Chapter 5
235

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