NEC V850ES/F 3-L Series User Manual page 161

Clock Generator
8 MHz internal
oscillator
Main system clock
fxx
PLL
(1)
Table 4-1
The high speed internal oscillator generates a clock f
typically 8 MHz. After reset release, the 8 MHz internal oscillator is activated.
The high speed internal oscillator is equipped with a stop control. The
oscillation can be stopped by means of the RCM register.
The main system clock fxx can be derived from different sources:
• Clock-through mode: main system clock f
internal oscillator f
RH
• PLL mode, main system clock f
These modes can be selected by the bit PLLCTL.SELPLL.
The PLL circuit generates the base frequency f
main system clock f .
xx
Input clock to the PLL the MainOSC f
The PLL is preceded by a frequency divider. The input of the PLL (f
set to f , f /2, or f /4. The divider is set through an option byte in the code flash
X X X
memory.
The phase-locked loop circuit (PLL) multiplies the MainOSC clock f
fraction of it by eight. Its input clock is called f
The PLL is started or stopped by PLLCTL.PLLON. For details on the PLL see
also "Controlling the PLL" on page 215.
System and CPU clocks
The CPU system is clocked by two clocks:
• f supplies all remaining parts of the CPU system, like BCU, MEMC,
VBCLK
INTC.
• f is derived from f
CPU
mode control.
Clock source for both clocks can be the output of the PLL or any of the
oscillators.
The following table gives an overview of the available CPU clock sources.
Clock sources for the CPU
Clock source Frequency
8 MHz internal ~8 MHz
oscillator
240 KHz internal ~240 KHz
oscillator
SubOSC 32 KHz or 20 KHz Selectable as clock source.
MainOSC 4 to 16 MHz
PLL up to 20 MHz
User's Manual U18743EE1V2UM00
XX
.
derived from f
XX
.
x
PLLI
supplies the CPU core and is subject to HALT
VBCLK
Description
Default clock source after reset release.
Default clock source if MainOSC has
stopped.
CPU system clocks in clock-through mode
For maximum performance
Chapter 4
with a frequency of
RH
derived from MainOSC f
(PLL output).
PLLO
, which can be used as the
PLL
PLLI
or a
x
, its output is f .
PLLO
or
X
) can be
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