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Chapter 21 Reset
21.1 Overview
Features summary
21.1.1 General reset performance
Figure 21-1
Several reset functions are provided in order to initialize hardware and
registers.
An internal system reset SYSRES can be generated by the following sources:
• External reset signal RESET
• Power-On-Clear (RESPOC)
• Watchdog Timer 2 (RESWDT2)
• Clock Monitor (RESCLM)
• Low-Voltage Detector (RESLVI)
The following figure shows the signals involved in the reset function.
NPB
RESF
RESET
RESPOC
RESLVI
RESCLM
RESWDT2
Reset function signal diagram
All resets are applied asynchronously. That means, resets are not
synchronized to any internal clock. This ensures that the microcontroller can
be kept in reset state even if all internal clocks fail to operate.
User's Manual U18743EE1V2UM00
WDT2
0
0
0
0
0
CLMRF
LVIRF
RF
RESF = 00
H
SYSRES
705
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