NEC V850ES/F 3-L Series User Manual page 464

Chapter 17
SPIEn Enable/disable generation of interrupt request when stop condition is detected
0 Disabled
1 Enabled
Condition for clearing (SPIEn = 0)
• Cleared by instruction
• After reset
Note
WTIMn
Interrupt request is generated at the eighth clock's falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
0
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for the master
device.
Interrupt request is generated at the ninth clock's falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for the master
1
device. In order to generate the ninth clock on SCLn, the wait status must be cancelled by writing to
IICn or setting IICCn.WRELn = 1. Consequently the ninth clock will be delayed until the wait status
is cancelled.
During address transfer, an interrupt occurs at the falling edge of the ninth clock regardless of this bit setting. This
bit setting becomes valid when the address transfer is completed. In master mode, a wait is inserted at the falling
edge of the ninth clock during address transfer. For a slave device that has received a local address, a wait is
inserted at the falling edge of the ninth clock after an ACK signal is issued. When the slave device has received
an extension code, however, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIMn = 0)
• Cleared by instruction
• After reset
ACKEn
0 Acknowledgment disabled.
1 Acknowledgment enabled. During the ninth clock period, the SDA0n line is set to low level.
The ACKE0 bit setting is invalid for address reception. In this case, ACK is generated when the addresses match.
However, the ACKE0 bit setting is valid for reception of the extension code.
Condition for clearing (ACKEn = 0)
• Cleared by instruction
• After reset
Note
464
Note 2
1. The IICS register, IICFn.STCFn and IICFn.IICBSYn bits, and IICCLn.CLDn
and IICCLn.DADn bits are reset.
2. This flag's signal is invalid when the IICEn = 0.
Control of wait and interrupt request generation
Note
Acknowledgement control
Note
This flag's signal is invalid when the IICEn = 0.
User's Manual U18743EE1V2UM00
Condition for setting (SPIEn = 1)
• Set by instruction
Condition for setting (WTIMn = 1)
• Set by instruction
Condition for setting (ACKEn = 1)
• Set by instruction
2
I C Bus (IIC)
Note