Table of Contents
Advertisement
Chapter 14
Table 14-3
WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
×
1
Caution
388
Watchdog Timer 2 Clock Selection
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
×
×
×
1.
If the WDTM2 register is rewritten twice after reset, an overflow signal is
forcibly generated. If the Watchdog Timer has stopped operation, WDTM2
can be written several times without generating an overflow.
2.
To stop WDT2 securely,
•
stop the internal oscillator by RCM.RSTOP = 1
(must be permitted by flash mask options)
•
set WDTM2 = 1F
3.
In order to ensure that the Watchdog Timer does not overflow, and thus
generate a watchdog event, during the register settings are changed, write
to WDTE first for restarting the timer.
User's Manual U18743EE1V2UM00
Selected
clock period
12
2
/f
RL
13
2
/f
RL
14
2
/f
RL
15
2
/f
RL
16
2
/f
RL
17
2
/f
RL
18
2
/f
RL
19
2
/f
RL
(default)
16
2
/f
X
17
2
f
X
18
2
/f
X
19
2
/f
X
20
2
/f
X
21
2
/f
X
22
2
/f
X
23
2
/f
X
Stop
H
Watchdog Timer 2
240 KHz (typ.)
17.1 ms
34.1 ms
68.3 ms
136.5 ms
273.1 ms
546.1 ms
1,092.3 ms
2,184.5 ms
f
= 4 MHz
f
= 16 MHz
X
X
16.4 ms
4.1 ms
32.8 ms
8.2 ms
65.5 ms
16.4 ms
131.1 ms
32.8 ms
262.1 ms
65.3 ms
524.3 ms
131.1 ms
1,048.6 ms
262.2 ms
2,097.2 ms
524.3 ms
Advertisement
Table of Contents
