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Chapter 17
SCL0n
SDA0n
Figure 17-9
484
the ACKEn bit to 0 will prevent the master device from starting transmission of
the subsequent data.
Similarly, when the master device is receiving (when TRCn bit = 0) and the
subsequent data is not needed and when either a restart condition or a stop
condition should therefore be output, clearing the ACKEn bit to 0 will prevent
the ACK signal from being returned. This prevents the MSB from being output
via the SDA0n line (i.e., stops transmission) during transmission from the slave
device.
1
2
3
AD6
AD5
AD4
ACK signal
When the local address is received, an ACK signal is automatically output in
synchronization with the falling edge of the SCL0n pin's eighth clock
regardless of the value of the ACKEn bit. No ACK signal is output if the
received address is not a local address.
The ACK signal output method during data reception is based on the wait
timing setting, as described below.
When 8-clock wait is selected (IICCn.WTIMn bit = 0):
The ACK signal is output at the falling edge of the SCL0n pin's eighth clock
if the ACKEn bit is set to 1 before wait cancellation.
When 9-clock wait is selected (IICCn.WTIMn bit = 1):
The ACK signal is automatically output at the falling edge of the SCL0n
pin's eighth clock if the ACKEn bit has already been set to 1.
User's Manual U18743EE1V2UM00
4
5
6
7
AD3
AD2
AD1
AD0
2
I
C Bus (IIC)
8
9
R/W ACK
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