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7.3 Next Address Setting Function
The DMA source address registers (DSAHn, DSALn), DMA destination address registers (DDAHn,
DDALn), and DMA transfer count register (DBCn) are buffer registers with a 2-stage FIFO configuration.
When the terminal count is issued, these registers are automatically rewritten with the value that was
set immediately before.
Therefore, during DMA transfer, transfer is automatically started when a new DMA transfer setting is
made for these registers and the MLEn bit of the DCHCn register is set (however, the DMA transfer end
interrupt may be issued even if DMA transfer is automatically started).
Figure 7-14, "Buffer Register Configuration," on page 183 shows the configuration of the buffer register.
Remark:
n = 0 to 3
Chapter 7 DMA Functions (DMA Controller)
Figure 7-14: Buffer Register Configuration
Data read
Data write
Master
register
Preliminary User's Manual U15839EE1V0UM00
Address/
Slave
count
register
controller
183
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