Emi Constraints; Figure 124. Bclk To Gclkin Timing Requirement - Intel 855GM Design Manual

Platform Clock Routing Guidelines

Figure 124. BCLK to GCLKIN Timing Requirement

When assessing whether a system design meets the required BCLK/GCLKIN phase relationship, the
following factors should be taken into account:
• Selected clock synthesizer chip's worst case (minimum) phase relationship between CLK66
(GCLKIN) and HCLKx (BCLK) rising edges. This includes the following clock timing
parameters:


• Trace length difference between BCLK and GCLKIN routing.
• Board manufacturing variations affecting signal delay across clock traces.
• All relevant variables should be evaluated over the system's full specified operating temperature
range.
12.2.1.4.

EMI Constraints

Clocks are a significant contributor to EMI and should be treated with care. The following
recommendations can aid in EMI reduction:
• Maintain uniform spacing between the two halves of differential clocks.
• Route clocks on physical layer adjacent to the VSS reference plane only.
244
Min phase offset. Since the CK408 spec does not specify the phase offset between
CLK66 and CPUx, the actual worst case (min) offset must be determined by consulting with
the selected clock synthesizer chip's vendor.
Cycle-to-cycle jitter on each clock output. Max jitter is specified by the CK408 clock
spec, but may be less than the max specified for any particular CK408 compatible clock
synthesizer chip.
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Intel 855GM/855GME Chipset Platform Design Guide
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