Intel 855GM Design Manual page 329

A
4
3
Layout note: Place one cap close to every 2 pullup resistors terminated to +V1.25.
4,46 +V1.25S
2
C6W13 C5W29 C6W14 C5W19
0.01UF 0.01UF 0.1UF 0.1UF
C5W15 C5W26 C5H2 C6H4
0.1UF 0.1UF 0.01UF 0.01UF
C5W22 C5W33 C5W32 C5W25
0.01UF 0.1UF 0.01UF 0.01UF
C4W14 C5W34 C5W36 C4W15
1
0.1UF 0.01UF 0.01UF 0.01UF
C5W17 C4W7 C5W12 C5W30
0.1UF 0.01UF 0.01UF 0.01UF
A
B
C5W21 C5W11 C4W10 C4W6 C4H3
0.1UF 0.1UF 0.1UF 0.1UF 0.01UF
C4H4 C4W9 C5W10 C4W13 C5W37
0.1UF 0.01UF 0.01UF 0.01UF 0.1UF
C5H1 C6W11 C6W10 C5W35 C5W20
0.1UF 0.1UF 0.01UF 0.1UF 0.01UF
C4W11 C5W18 C6W12 C5W23 C4W8
0.01UF 0.01UF 0.1UF 0.1UF 0.1UF
C4W5 C5W38 C5W16 C4W4 C6H3
0.01UF 0.01UF 0.01UF 0.1UF 0.1UF
B
C
7,12,13 M_AA0
7,11 M_AA[2:1]
7,12,13 M_AA3
7,11 M_AA[5:4]
7,12,13 M_AA[12:6]
M_DATA_R_[63:0]
11..13 M_DATA_R_[63:0]
7,12,13 M_AA[12:6]
11..13 M_DQS_R[8:0]
C5W28 C5W14 C4W16
0.1UF 0.01UF 0.1UF
C6W9 C4W12 C5W39
0.1UF 0.1UF 0.01UF
C5W31 C5W13 C5W24
0.1UF 0.1UF 0.01UF
C4H2 C5W27 C5W7
11..13 M_DM_R_[8:0]
0.1UF 0.01UF 0.1UF
C6H5 C5W8 C5W9
0.1UF 0.1UF 0.1UF
C
D
7,11,12 M_CKE0
7,11,12 M_CKE1
7,11,12 M_CS0#
7,11,12 M_CS1#
M_DQS_R[8:0]
7,12 M_CS2#
7,12 M_CS3#
7,12 M_CKE3
7,12 M_CKE2
7,12,13 M_BS0#
7,12,13 M_BS1#
7,12,13 M_WE#
7,12,13 M_RAS#
44,46 +V1.25S
7,12,13 M_CAS#
56 56 56 56 56 56 56 56
Title
DDR Parallel Termination
Size Project:
A Intel 855GM/GME CRB
Date: Monday, September 15, 2003
D
E
44,46 +V1.25S
M_CB_R[7:0] 11..13
4
3
2
7,12 M_AB5
7,12 M_AB4
7,12 M_AB2
7,12 M_AB1
1
Document Number Rev
4.401
<Doc>
50
Sheet 14 of
E