V Power Delivery Guidelines; Gmch And Ddr Smvref Design Recommendations; Figure 139. Ddr Power Delivery Block Diagram - Intel 855GM Design Manual

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• JEDEC Standard, JESD79 (release 2), Double Data Rate (DDR) SDRAM Specification
• Intel DDR 266 JEDEC Spec Addendum Rev 1.0 or later

Figure 139. DDR Power Delivery Block Diagram

NOTE: +V1.25 used for VTT can optionally be on the switched rail and turned off in S3.
13.5.2.1.

2.5-V Power Delivery Guidelines

The 2.5-V power for the GMCH system memory interface and the DDR SO-DIMMs is delivered around
the DDR command, control, and clock signals. Special attention must be paid to the 2.5-V copper
flooding to ensure proper GMCH and SO-DIMM power delivery. This 2.5-V flood must extend from
the GMCH 2.5-V power vias all the way to the 2.5-V DDR voltage regulator and its bulk capacitors.
The 2.5-V DDR voltage regulator must connect to the 2.5-V flood with a minimum of six vias. The SO-
DIMM connector 2.5-V pins as well as the GMCH 2.5-V power vias must connect to the 2.5-V copper
flood.
In the areas where the copper flooding necks down around the GMCH, make sure to keep these neck
down lengths as short as possible. The 2.5-V copper flooding under the SO-DIMM connectors must
encompass all the SO-DIMM 2.5-V pins and must be solid except for the small areas where the clocks
are routed within the SO-DIMM pin field to their specified SO-DIMM pins.
Note: A minimum of 12-mil isolation spacing should be maintained between the copper flooding and any
signals on the same layer.
13.5.2.2.

GMCH and DDR SMVREF Design Recommendations

There is one SMVREF pin on the GMCH that are used to set the reference voltage level for the DDR
system memory signals (SMVREF). The voltage level that needs to be supplied to these pins must be
equal to VCCSM/2. As shown in Figure 139 an OpAmp buffer is recommended to generate SMVREF
from the 2.5-V supply. This should be used as the "VREF" signals to both the DDR memory devices
and the SMVREF signal to the GMCH. A resistor divider is not a recommended solution since
SMVREF has a tight tolerance of ± 2%.
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Intel 855GM/855GME Chipset Platform Design Guide
Intel 855GM/GME Chipset Based System Power Delivery Guidelines
+ V 5
S w itc h in g
R e g u la t o r
V in
1 0 K
1 0 K
+ V 5
S w itc h i n g
R e g u la t o r
V in
V o u t
S e n s e A d j.
+
-
V o u t
S e n s e A d j.
+ V 2 _ 5
S M V R E F
+ V 1 _ 2 5 S
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