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SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
Voltage Rails
4
+VDC
Primary DC system power supply (10 to 21V)
+VCC_CORE
Core voltage for processor
+VCCP
1.05V rail for processor PSB, 855GME PSB
+V1.8S
1.8V for processor PLL and VID circuitry
+V1.25S
1.25V DDR Termination voltage
1.35V for 855GM core
+V1.35S
1.5V switched power rail (off in S3-S5)
+V1.5S
1.5V always on power rail
+V1.5ALWAYS
+V1.5
1.5V power rail (off in S4-S5)
+V2.5
2.5V power rail for DDR
3.3V always on power rail
+V3.3ALWAYS
3.3V power rail (off in S4-S5)
+V3.3
3.3V switched power rail (off in S3-S5)
+V3.3S
5.0V for ICH4M's VCC5REFSUS
+V5ALWAYS
5.0V power rail (off in S4-S5)
+V5
3
5.0V switched power rail (off in S3-S5)
+V5S
12.0V switched power rail (off in S3-S5)
+V12S
-12.0V switched power rail for PCI (off in
-V12S
S3-S5)
PCI Devices
Device
IDSEL #
Slot 1
AD16
Slot 2
AD17
Slot 3
AD18
Docking
AD28
LAN
(AD24 internal)
Net Naming Conventions
2
Suffix
# = Active Low Signal
Prefix
H = Host
TP = Test Point (does not
M = DDR Memory
Power States
SIGNAL
STATE
SLP_S1#
Full ON
HIGH
S1M (Power On Suspend)
LOW
1
S3 (Suspend to RAM)
LOW
S4 (Suspend To Disk)
LOW
S5 / Soft OFF
LOW
A
B
Intel 855GM/GME CUSTOMER REFERENCE PLATFORM
REQ/GNT #
Interrupts
PC/PCI
1
1
F, G, H, E
A
2
2
G, F, E, H
A
3
3
C, D, B, A
A
(E, F, G, H optional)
4
4
B, C, D, A
B
A, B
connect anywhere else)
SLP_S3#
SLP_S4#
SLP_S5#
+V*ALWAYS
+V*
HIGH
HIGH
HIGH
ON
ON
HIGH
HIGH
HIGH
ON
ON
LOW
HIGH
HIGH
ON
ON
LOW
LOW
HIGH
ON
OFF
LOW
LOW
LOW
ON
OFF
B
C
2
I C / SMB Addresses
Device
Address
Hex
Bus
Clock Generator
1101 001x
D2
SMB_ICH_S
Spread Spectrum Clock
1101 010x
D4
SMB_ICH_S
SO-DIMM0
1010 000x
A0
SMB_ICH_S
SO-DIMM1
1010 001x
A2
SMB_ICH_S
Thermal Sensor Header
1001 000x
90
SMB_ICH
LVDS Backlight Inverter
____ ____
__
SMB_ICH
Dock Connector
____ ____
__
SMB_ICH
Smart Battery
0001 011x
16
SMB_SB
Smart Battery Charger
0001 001x
12
SMB_SB
Smart Selector
0001 010x
14
SMB_SB
Bluetooth Header
____ ____
__
SMB_SB
LPC Pwr Mngmnt Header
____ ____
__
SMB_SB
LPC Pwr Mngmnt Header
____ ____
__
SMB_THRM
Thermal Diode
1001 110x
9C
SMB_THRM
EV Support:
DV0-DV3
0101 0001
51
SMB_ICH
V5-V8
0101 0010
52
SMB_ICH
PV0-PV3
0101 0011
53
SMB_ICH
DV4
0101 0100
54
SMB_ICH
V9-V12
0101 0101
55
SMB_ICH
I1-I4
0101 0110
56
SMB_ICH
EP1-EP4
0101 0111
57
SMB_ICH
PV4
0101 0100
58
SMB_ICH
V1-V4
0101 1001
59
SMB_ICH
LEDs and Switches
LED
Page
Primary IDE
27
Secondary IDE
27
SMC/KBC Num Lock
32
SMC/KBC Scroll Lock
32
SMC/KBC Caps Lock
32
VID0
34
VID1
34
VID2
34
VID3
34
VID4
34
VID5
34
S0 State
38
S1 State
38
S3 State
38
S4 State
38
S5 State
38
Switch
Page
Virtual Battery On/Off
32
Lid
32
Power On/Off
45
Reset
45
+V*S
Clocks
ON
ON
ON
LOW
OFF
OFF
OFF
OFF
OFF
OFF
C
D
Default Jumper Settings
Jumper
Default
Option
J7B2
1-X
1-2
J7B3
1-X
1-2
J7B4
1-2
1-X
J7B5
1-2
1-X
J7C1
1-2
1-X
J6E1
2-3
1-2
J6D1
1-X
1-2
J4F1
1-X
1-2
J2J3
1-X
1-2
J8J2
2-3
1-2
J9E2
1-2
2-3
J9E4
1-2
2-3
J9E5
2-3
1-2
J9B1
1-X
1-2
J8A2
1-2
2-3
J9A1
1-X
1-2
J9A3
1-X
1-2
J8A1
1-2
1-X
J9H1
1-X
1-2
J9G2
1-2
2-3
J3G1
1-X
1-2
J1H4
1-X
1-2
J1H5
1-X
1-2
Wake Events
Reference
RI# (Ring Indicate) from serial port
DS2J2
PME# (Power Management Event) from PCI/mini-PCI slots,
DS2J1
ADD slot, LPC slot
DS8A1
LAN Connect Interface from 82562EM
DS8A2
LID switch attached to SMC
DS8B1
DS1J1
USB
DS1J2
AC97 wake on ring
DS1J3
SmLink for AOL II
DS1J4
Hot Key from the scan matrix keyboard
DS2J3
DS2J4
DS1H1
DS1H3
PCB Footprints
DS1H2
DS2H2
DS2H1
SOT-23
1
Reference
SW8A1
SW9A1
3
SW8J1
As seen from top
SW7J1
2
Title
Notes and Annotations
Size
Project:
A
Intel 855GM/GME CRB
Date:
Monday, September 15, 2003
D
E
4
Description
Page
GMCH Strap: PSB Voltage
08
GMCH Strap: DVO Strap
08
GMCH Strap: Clock Config
08
GMCH Strap: Clock Config
08
GMCH Strap: Clock Config
08
LVDS EV
08
No-Shunt Default
09
No-Shunt Default
09
CMOS Clear
19
CRB/SV Detect
19
Moon ISA Support
23
Moon ISA Support
23
Moon ISA Support
23
SMC/KBC Programming
32
SMC/KBC Disable
32
KBC 60/64 Decode Disable
32
SMC_LID Disable
32
NMI Jumper
33
Port 80-81/82-83 Select
33
SIO Disable
34
DDR EV Support
44
A_FAN_P1
46
3
A_FAN_P0
46
2
SOT23-5
1
5
2
3
4
1
Document Number
Rev
<Doc>
4.401
Sheet
2
of
50
E
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