Slowport Signals; Topology And Routing; Signal Description - Intel IXP28XX Manual

IXP28XX Network Processor
Slowport
7.1.1
Table 47.
7.1.1.1
7.1.1.1.1
130
Downloaded from Elcodis.com electronic components distributor

Slowport Signals

The Slowport signals are defined in

Signal Description

Signal Name
SP_AD[7:0] Address and Data multiplexed bidirectional tri-state busses
SP_OE_L Output enable for external buffer
SP_CP/SP_A0 Latch enable for 16- or 32-bit data bus devices. Address [0] for 8-bit devices. O
Data transaction direction. Low for read, High for write.
SP_DIR/SP_A1
Address [1] for 8-bit devices
SP_ALE_L Address latch enable
Device Selects:
SP_CS[0] Lower 32-Mbyte address spaces used for FLASH.
SP_CS[1:0]
SP_CS[1] Upper 32-Mbyte address space used for Microprocessor type
devices.
SP_RD_L Read strobe
SP_WR_L Write Strobe
SP_ACK Acknowledge signal
SP_CLK Clock

Topology and Routing

The following sections describe the topology and routing guidelines for Slowport interface control
signals, clocks, and address/data signals.
Slowport Control Signals
Figure 78 illustrates the Slowport control signals topology.
Table 47; Slowport signals use LVTTL signal levels.
Description I/O
I/O
O
O
O
O
O
O
I
O
Hardware Design Guide