Intel 855GM Design Manual page 7

R
9.2.5.
9.2.6.
9.2.7.
9.2.8.
9.2.9.
9.2.10.
9.2.11.
10. Hub Interface ............................................................................................................................187
10.1. Hub Interface Compensation .......................................................................................187
10.2. Hub Interface Data HL[10:0] and Strobe Signals ........................................................188
10.2.1.
10.2.2.
10.3. Hub VREF/VSWING Generation/Distribution ..............................................................190
10.3.1.
10.3.2.
10.3.3.
10.3.4.
10.4. Hub Interface Decoupling Guidelines ..........................................................................193
11. I/O Subsystem ..........................................................................................................................195
11.1. IDE Interface ................................................................................................................195
11.1.1.
11.1.2.
11.1.3.
11.1.4.
11.2. PCI
11.3. AC'97
11.3.1.
11.3.2.
11.3.3.
11.4. USB 2.0 Guidelines and Recommendations ...............................................................206
11.4.1.
11.4.2.
11.4.3.
11.4.4.
11.4.5.
Intel® 855GM/855GME Chipset Platform Design Guide
AGP Interface Package Lengths..................................................................183
AGP Routing Ground Reference .................................................................184
Pull-ups ........................................................................................................184
AGP VDDQ and VCC...................................................................................186
VREF Generation for AGP 2.0 (2X and 4X).................................................186
9.2.9.1. 1.5-V AGP Interface (2X/4X).........................................................186
AGP Compensation .....................................................................................186
PM_SUS_CLK/AGP_PIPE# Design Consideration.....................................186
HL[10:0] and Strobe Signals Internal Layer Routing ...................................188
Terminating HL[11].......................................................................................190
Single Generation Voltage Reference Divider Circuit..................................190
Locally Generated Voltage Reference Divider Circuit .................................191
Single GMCH and ICH4-M Voltage Generation / Separate Divider
Circuit for VSWING/VREF............................................................................192
Separate GMCH and ICH4-M Voltage Generation / Separate Divider
Circuits for VREF and VSWING...................................................................193
Cabling .........................................................................................................195
Primary IDE Connector Requirements.........................................................196
Secondary IDE Connector Requirements....................................................197
Mobile IDE Swap Bay Support.....................................................................198
11.1.4.1. ICH4-M IDE Interface Tri-State Feature .......................................198
11.1.4.2. S5/G3 to S0 Boot Up Procedures for IDE Swap Bay ...................199
11.1.4.3. Power Down Procedures for Mobile Swap Bay ............................199
11.1.4.4. Power Up Procedures After Device "Hot" Swap Completed ........199
200
200
AC'97 Routing ..............................................................................................204
Motherboard Implementation .......................................................................205
11.3.2.1. Valid Codec Configurations ..........................................................205
SPKR Pin Configuration...............................................................................205
Layout Guidelines ........................................................................................206
11.4.1.1. General Routing and Placement...................................................206
11.4.1.2. USB 2.0 Trace Separation ............................................................207
11.4.1.3. USBRBIAS Connection.................................................................207
11.4.1.4. USB 2.0 Termination.....................................................................208
11.4.1.5. USB 2.0 Trace Length Pair Matching ...........................................208
11.4.1.6. USB 2.0 Trace Length Guidelines ................................................208
Plane Splits, Voids, and Cut-Outs (Anti-Etch)..............................................208
11.4.2.1. VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)......................209
11.4.2.2. GND Plane Splits, Voids, and Cut-Outs (Anti-Etch) .....................209
USB Power Line Layout Topology ...............................................................209
EMI Considerations......................................................................................210
11.4.4.1. Common Mode Chokes ................................................................210
ESD ..............................................................................................................211
7