Format Of Watchdog Timer Enable Register (Wdte) - NEC 78K0 User Manual

Cautions 1. If data is written to WDTM, a wait cycle is generated. Do not write data to WDTM
when the CPU is operating on the subsystem clock and the X1 input clock is
stopped. For details, see CHAPTER 35 CAUTIONS FOR WAIT.
2. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when "Ring-OSC cannot be stopped"
is selected by a mask option, other values are ignored).
3. After reset is released, WDTM can be written only once by an 8-bit memory
manipulation instruction. If writing attempted a second time, an internal reset signal
is generated.
4. WDTM cannot be set by a 1-bit memory manipulation instruction.
Remarks 1. f
R
2. f
XP
3. ×: Don't care
4. Figures in parentheses apply to operation at f
(2) Watchdog timer enable register (WDTE)
Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to 9AH.
Figure 11-3. Format of Watchdog Timer Enable Register (WDTE)
Address: FF99H After reset: 9AH
7
Symbol
WDTE
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated.
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated.
3. The value read from WDTE is 9AH (this differs from the written value (ACH)).
266
CHAPTER 11 WATCHDOG TIMER
: Ring-OSC clock oscillation frequency
: X1 input clock oscillation frequency
R/W
6 5 4
User's Manual U15947EJ2V0UD
= 240 kHz (TYP.), f
R
3 2 1
*
= 10 MHz
XP
0