Operation In Stop Mode (Cpu Clock: Ring-Osc Clock, Wdt Operation Clock: X1 Input Clock) - NEC 78K0 User Manual

(3) When the CPU clock is the Ring-OSC clock (f
clock (f ) when the STOP instruction is executed
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When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started
using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds
its value.
<1> The oscillation stabilization time set by the oscillation stabilization time select register (OSTS) elapses.
<2> The CPU clock is switched to the X1 input clock (f
(CPU Clock: Ring-OSC Clock, WDT Operation Clock: X1 Input Clock)
<1> Timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time
select register (OSTS) has elapsed
Normal operation
(Ring-OSC clock)
CPU operation
f
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f
R
Watchdog timer
Operating
<2> Timing when counting is started after the CPU clock is switched to the X1 input clock (f
Normal operation
(Ring-OSC clock)
CPU operation
f
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f
R
Watchdog timer
Operating
Note Confirm the oscillation stabilization time of f
(OSTC).
270
CHAPTER 11 WATCHDOG TIMER
) and the watchdog timer operation clock is the X1 input
R
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Figure 11-6. Operation in STOP Mode
STOP Clock supply stopped
Oscillation Oscillation stabilization time
stopped (set by OSTS register)
*
17 clocks
Operation stopped
Normal operation (Ring-OSC clock)
Clock supply
STOP
stopped
Oscillation Oscillation stabilization time
stopped (set by OSTS register)
17 clocks
Operation stopped
using the oscillation stabilization time counter status register
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User's Manual U15947EJ2V0UD
).
Normal operation (Ring-OSC clock)
CPU clock
→ f
Note
f
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Normal operation (X1 input clock)
Operating
)
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Operating