Chapter 23 Clock Monitor; Functions Of Clock Monitor; Configuration Of Clock Monitor - NEC 78K0 User Manual

23.1 Functions of Clock Monitor

The clock monitor samples the X1 input clock using the on-chip Ring-OSC, and generates an internal reset signal
when the X1 input clock is stopped.
When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set
to 1. For details of RESF, see CHAPTER 22 RESET FUNCTION.
The clock monitor automatically stops under the following conditions.
• Reset is released and during the oscillation stabilization time
• In STOP mode and during the oscillation stabilization time
• When the X1 input clock is stopped by software (MSTOP = 1 or MCC = 1) and during the oscillation stabilization
time
• When the Ring-OSC clock is stopped
Remark MSTOP: Bit 7 of main OSC control register (MOC)
MCC: Bit 7 of processor clock control register (PCC)

23.2 Configuration of Clock Monitor

Clock monitor consists of the following hardware.
Item
Control register Clock monitor mode register (CLM)
X1 oscillation control signal
(MCC, MSTOP)
X1 oscillation stabilization status
(OSTC overflow)
Remark MCC: Bit 7 of processor clock control register (PCC)
MSTOP: Bit 7 of main OSC control register (MOC)
OSTC: Oscillation stabilization time counter status register (OSTC)

CHAPTER 23 CLOCK MONITOR

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Table 23-1. Configuration of Clock Monitor
Configuration
Figure 23-1. Block Diagram of Clock Monitor
Internal bus
Clock monitor
mode register (CLM)
CLME
Operation mode
controller
X1 input clock
Ring-OSC clock
User's Manual U15947EJ2V0UD
X1 oscillation
Internal reset
monitor circuit signal
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