NEC 78K0 User Manual page 623

Edition
1st edition Modification of the following contents in CHAPTER 30 ELECTRICAL SPECIFICATIONS
(Modified (TARGET VALUES)
version) • Absolute Maximum Ratings
• X1 Oscillator Characteristics
• Subsystem Clock Oscillator Characteristics
• DC Characteristics
• A/D Converter Characteristics
• POC Circuit Characteristics
• LVI Circuit Characteristics
• Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(deletion of data retention supply current)
• Deletion of Ring-OSC Characteristics
• Flash Memory Programming Characteristics
Modification from CHAPTER 32 RETRY to CHAPTER 32 CAUTIONS FOR WAIT
Addition of products
2nd edition
µ
PD78F0148(A1), 780143(A2), 780144(A2), 780146(A2), 780148(A2)
Under development → Under mass production
µ
PD780143, 780144, 780146, 780148, 78F0148, 780143(A), 780144(A), 780146(A),
780148(A), 78F0148(A), 780143(A1), 780144(A1), 780146(A1), 780148(A1)
Modification of names of the following special function registers (SFRs)
• Ports 0 to 7, and 12 to 14 → Port registers 0 to 7, and 12 to 14
Addition of Cautions 3 and 4 to 1.4 Pin Configuration (Top View)
Modification of 1.5 K1 Family Lineup
Modification of outline of timer in and addition of Remark to 1.7 Outline of Functions
Addition of Table 2-1 Pin I/O Buffer Power Supplies
Modification of descriptions in 2.2.12 AV
memory versions only)
Modification of the following contents in Table 2-2 Pin I/O Circuit Types
• Modification of recommended connection when P60 to P63 are not used
• Modification of I/O circuit type of P62 and P63
• Addition of Note to AV
• Modification of recommended connection when V
Modification of Figure 3-1 Memory Map (
µ
( PD78F0148)
Modification of Figure 3-14 Data to Be Saved to Stack Memory
Modification of Figure 3-15 Data to Be Restored from Stack Memory
Modification of [Description example] in 3.4.4 Short direct addressing
Addition of [Illustration] to 3.4.7 Based addressing, 3.4.8 Based indexed
addressing, and 3.4.9 Stack addressing
Addition of Table 4-1 Pin I/O Buffer Power Supplies
Modification of Table 4-3 Port Configuration
Modification of Figure 4-11 Block Diagram of P20 to P27, Figure 4-14 Block Diagram
of P40 to P47, Figure 4-15 Block Diagram of P50 to P57, Figure 4-17 Block Diagram
of P64, P65, and P67, and Figure 4-18 Block Diagram of P66
Addition of Remark to Figure 4-21 Block Diagram of P130
APPENDIX D REVISION HISTORY
Description
*
, 2.2.15 REGC, and 2.2.20 V
REF
REF
is not used
PP
µ
PD780143) to Figure 3-5 Memory Map
User's Manual U15947EJ2V0UD
Applied to:
CHAPTER 30
ELECTRICAL
SPECIFICATIONS
(TARGET VALUES)
CHAPTER 32
CAUTIONS FOR WAIT
Throughout
CHAPTER 1 OUTLINE
CHAPTER 2 PIN
FUNCTIONS
(flash
PP
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
(2/5)
623