NEC 78K0 User Manual page 520

Instruction
Mnemonic
Group
8-bit SUB A, #byte
operation
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
SUBC A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
AND A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
520
CHAPTER 29 INSTRUCTION SET
Clocks
Operands Bytes
Note 1
2 4
3 6
Note 3
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
2 4
3 6
Note 3
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
2 4
3 6
Note 3
2 4
2 4
2 4
3 8
1 4
2 8
2 8
2 8
User's Manual U15947EJ2V0UD
Operation
Note 2
− A, CY ← A − byte
(saddr), CY ← (saddr) − byte
8
− A, CY ← A − r
− r, CY ← r − A
A, CY ← A − (saddr)
5
A, CY ← A − (addr16)
9 + n
A, CY ← A − (HL)
5 + n
A, CY ← A − (HL + byte)
9 + n
A, CY ← A − (HL + B)
9 + n
A, CY ← A − (HL + C)
9 + n
− A, CY ← A − byte − CY
(saddr), CY ← (saddr) − byte − CY
8
− A, CY ← A − r − CY
− r, CY ← r − A − CY
A, CY ← A − (saddr) − CY
5
A, CY ← A − (addr16) − CY
9 + n
A, CY ← A − (HL) − CY
5 + n
A, CY ← A − (HL + byte) − CY
9 + n
A, CY ← A − (HL + B) − CY
9 + n
A, CY ← A − (HL + C) − CY
9 + n
− A ← A ∧ byte
*
(saddr) ← (saddr) ∧ byte
8
− A ← A ∧ r
− r ← r ∧ A
A ← A ∧ (saddr)
5
A ← A ∧ (addr16)
9 + n
A ← A ∧ (HL)
5 + n
A ← A ∧ (HL + byte)
9 + n
A ← A ∧ (HL + B)
9 + n
A ← A ∧ (HL + C)
9 + n
) selected by the processor clock
CPU
Flag
Z AC CY
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
×
×
×
×
×
×
×
×
×
×