Format Of Clock Output Selection Register (Cks) - NEC 78K0 User Manual

Figure 12-2. Format of Clock Output Selection Register (CKS)
Address: FF40H After reset: 00H
Symbol <7>
CKS BZOE
BZOE
0
1
BCS1
0
0
1
1
CLOE
0
1
CCS3
0
0
0
0
0
0
0
0
1
Remarks 1. f : X1 input clock oscillation frequency
X
2. f : Subsystem clock oscillation frequency
XT
3. Figures in parentheses are for operation with f
274
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
R/W
6 5
BCS1 BCS0
BUZ output enable/disable specification
Clock division circuit operation stopped. BUZ fixed to low level.
Clock division circuit operation enabled. BUZ output enabled.
BCS0
10
0 f /2 (9.77 kHz)
X
11
1 f /2 (4.88 kHz)
X
12
0 f /2 (2.44 kHz)
X
13
1 f /2 (1.22 kHz)
X
PCL output enable/disable specification
Clock division circuit operation stopped. PCL fixed to low level.
Clock division circuit operation enabled. PCL output enabled.
CCS2 CCS1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
0 0
Other than above
User's Manual U15947EJ2V0UD
<4> 3 2
CLOE CCS3 CCS2
BUZ output clock selection
CCS0 PCL output clock selection
0 f (10 MHz)
X
*
1 f /2 (5 MHz)
X
2
0 f /2 (2.5 MHz)
X
3
1 f /2 (1.25 MHz)
X
4
0 f /2 (625 kHz)
X
5
1 f /2 (312.5 kHz)
X
6
0 f /2 (156.25 kHz)
X
7
1 f /2 (78.125 kHz)
X
0 f (32.768 kHz)
XT
Setting prohibited
= 10 MHz or f = 32.768 kHz.
X XT
1 0
CCS1 CCS0