NEC 78K0 User Manual page 24

Figure No.
11-1 Block Diagram of Watchdog Timer .........................................................................................................264
11-2 Format of Watchdog Timer Mode Register (WDTM)...............................................................................265
11-3 Format of Watchdog Timer Enable Register (WDTE) .............................................................................266
11-4 Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock)...............................269
11-5 Operation in STOP Mode (CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock)........269
11-6 Operation in STOP Mode (CPU Clock: Ring-OSC Clock, WDT Operation Clock: X1 Input Clock).........270
11-7 Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock) ............................271
11-8 Operation in HALT Mode ........................................................................................................................271
12-1 Block Diagram of Clock Output/Buzzer Output Controller.......................................................................272
12-2 Format of Clock Output Selection Register (CKS) ..................................................................................274
12-3 Format of Port Mode Register 14 (PM14) ...............................................................................................275
12-4 Remote Control Output Application Example..........................................................................................276
13-1 Block Diagram of A/D Converter.............................................................................................................277
13-2 Format of A/D Converter Mode Register (ADM) .....................................................................................281
13-3 Timing Chart When Boost Reference Voltage Generator Is Used ..........................................................282
13-4 Format of Analog Input Channel Specification Register (ADS)...............................................................283
13-5 Format of A/D Conversion Result Register (ADCR) ...............................................................................284
13-6 Format of Power-Fail Comparison Mode Register (PFM) .......................................................................285
13-7 Format of Power-Fail Comparison Threshold Register (PFT).................................................................285
13-8 Basic Operation of A/D Converter...........................................................................................................287
13-9 Relationship Between Analog Input Voltage and A/D Conversion Result ...............................................288
13-10 A/D Conversion Operation ......................................................................................................................289
13-11 Power-Fail Detection (When PFEN = 1 and PFCM = 0) .........................................................................290
13-12 Overall Error ...........................................................................................................................................292
13-13 Quantization Error...................................................................................................................................292
13-14 Zero-Scale Error
13-15 Full-Scale Error.......................................................................................................................................293
13-16 Integral Linearity Error
13-17 Differential Linearity Error .......................................................................................................................293
13-18 Circuit Configuration of Series Resistor String........................................................................................294
13-19 Analog Input Pin Connection ..................................................................................................................295
13-20 Timing of A/D Conversion End Interrupt Request Generation ................................................................296
13-21 Timing of A/D Converter Sampling and A/D Conversion Start Delay ......................................................297
13-22 Internal Equivalent Circuit of ANIn Pin ....................................................................................................298
14-1 Block Diagram of Serial Interface UART0...............................................................................................301
14-2 Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0)......................................303
14-3 Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0)............................305
14-4 Format of Baud Rate Generator Control Register 0 (BRGC0) ................................................................306
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