NEC 78K0 User Manual page 384

Note
ERRE0
0
Error detection disabled
1 Error detection enabled
ERRF0
0
• Bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) = 0
• At reset input
• When communication is started by setting bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) to 1
or writing to SIOA0.
1
Bit error detected (when ERRE0 = 1, the level specified by BUSYLV0 during the data bit transfer
period is detected via BUSY0 pin input).
TSF0
0
• Bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) = 0
• At reset input
• At the end of the specified transfer
• When transfer is stopped by setting bit 1 (ATSTP0) of serial trigger register 0 (CSIT0) to 1
1
From the transfer start to the end of the specified transfer
Note The ERRE0 setting is valid even when BUSYE0 = 0.
Caution When TSF0 is 1, rewriting serial operation mode specification register 0 (CSIMA0), serial status
register 0 (CSIS0), divisor selection register 0 (BRGCA0), automatic data transfer address point
specification register 0 (ADTP0), automatic data transfer interval specification register 0
(ADTI0), and serial I/O shift register 0 (SIOA0) are prohibited. However, these registers can be
read and re-written to the same value. In addition, the buffer RAM can be rewritten during
transfer.
384
CHAPTER 17 SERIAL INTERFACE CSIA0
Figure 17-4. Format of Serial Status Register 0 (CSIS0) (2/2)
Bit error detection enable/disable
Transfer status detection flag
User's Manual U15947EJ2V0UD
Bit error detection flag
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