NEC 78K0 User Manual page 451

(2) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait
time set by OSTS is valid only after STOP mode is released when the X1 input clock is selected as the CPU
clock. After STOP mode is released when the Ring-OSC clock is selected, check the oscillation stabilization time
using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 05H.
Figure 21-2. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H After reset: 05H
Symbol 7
OSTS 0
OSTS2
0
0
0
1
1
Cautions 1. If the STOP mode is entered and then released while the Ring-OSC clock is
Remarks 1. Values in parentheses are reference value for operation with f
CHAPTER 21 STANDBY FUNCTION
R/W
6 5
0 0
OSTS1 OSTS0
0 1
1 0
1 1
0 0
0 1
Other than above
being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
The X1 oscillation stabilization time counter counts only during the oscillation
stabilization time set by OSTS. Therefore, note that only the statuses during the
oscillation stabilization time set by OSTS are set to OSTC after STOP mode has
been released.
2. The wait time when STOP mode is released does not include the time after
STOP mode release until clock oscillation starts ("a" below) regardless of
whether STOP mode is released by RESET input or interrupt generation.
STOP mode release
X1 pin voltage
waveform
2. f : X1 input clock oscillation frequency
X
User's Manual U15947EJ2V0UD
4 3
0 0 OSTS2
Oscillation stabilization time selection
µ
11
2 /f (204.8 s)
X
µ
13
2 /f (819.2 s)
X
14
2 /f (1.64 ms)
X
15
2 /f (3.27 ms)
X
16
2 /f (6.55 ms)
X
Setting prohibited
*
a
2 1 0
OSTS1 OSTS0
= 10 MHz.
X
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