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12.3 Watchdog Timer Control Register
The registers to control the watchdog timer is shown below.
• Watchdog timer clock selection register (WDCS)
• Watchdog timer mode register (WDTM)
(1)
Watchdog timer clock selection register (WDCS)
This register selects the overflow times of the watchdog timer.
WDCS is set by an 8-bit memory manipulation instruction.
Figure 12-2: Watchdog Timer Clock Selection Register (WDCS)
7
6
WDCS
0
0
WDCS2
0
0
0
0
1
1
1
1
Note: This are only 2 examples for f
main oscillator resonators (4 or 5 MHz).
Chapter 12 Watchdog Timer Function
5
4
3
0
0
0
WDCS1
WDCS0
Clock
13
0
0
2
14
0
1
2
15
1
0
2
16
1
1
2
17
0
0
2
18
0
1
2
19
1
0
2
21
1
1
2
. The clock depends on the clock tree settings and the external
WD
Preliminary User's Manual U15839EE1V0UM00
2
1
0
WDCS2 WDCS1 WDCS0 FFFF F571H
Overflow Time
f
= f
WD
X
4 MHz (main clock)
/f
2 ms
WD
4.1 ms
/f
WD
8.2 ms
/f
WD
16.4 ms
/f
WD
/f
32.8 ms
WD
/f
65.5 ms
WD
131 ms
/f
WD
524 ms
/f
WD
Address
R/W
After reset
R/W
Note
f
= f
WD
XT
32 KHz (sub clock)
256 ms
512 ms
1.02 s
2.05 s
4.10 s
8.20 s
16.38 s
65.54 s
00H
359
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