Transmission Completion Interrupt Request Timing - NEC 78K0 User Manual

8-bit single-chip microcontrollers
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(c) Transmission
The T
D0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface operation mode
X
register 0 (ASIM0) is set to 1.
Transmission can be started by writing transmit data to transmit shift register 0 (TXS0). The start bit, parity
bit, and stop bit are automatically appended to the data.
When transmission is started, the start bit is output from the T
order starting from the LSB. When transmission is completed, the parity and stop bits set by ASIM0 are
appended and a transmission completion interrupt request (INTST0) is generated.
Transmission is stopped until the data to be transmitted next is written to TXS0.
Figure 14-8 shows the timing of the transmission completion interrupt request (INTST0). This interrupt
occurs as soon as the last stop bit has been output.
Caution After transmit data is written to TXS0, do not write the next transmit data before the
transmission completion interrupt signal (INTST0) is generated.
Figure 14-8. Transmission Completion Interrupt Request Timing
1. Stop bit length: 1
T
D0 (output)
X
INTST0
2. Stop bit length: 2
T
D0 (output)
X
INTST0
312
CHAPTER 14 SERIAL INTERFACE UART0
If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled.
Start
D0
D1
D2
Start
D0
D1
D2
User's Manual U15947EJ2V0UD
D0 pin, followed by the rest of the data in
X
Parity
D6
D7
*
D6
D7
Parity
Stop
Stop

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