Format Of Serial Operation Mode Specification Register 0 (Csima0) - NEC 78K0 User Manual

(1) Serial operation mode specification register 0 (CSIMA0)
This is an 8-bit register used to control the serial communication operation.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 17-3. Format of Serial Operation Mode Specification Register 0 (CSIMA0)
Address: FF90H
Symbol
CSIMA0
Note Automatic data transfer address count register 0 (ADTC0), serial trigger register 0 (CSIT0), serial I/O
shift register 0 (SIOA0), and bit 0 (TSF0) of serial status register 0 (CSIS0) are reset.
Cautions 1. When CSIAE0 = 0, the buffer RAM cannot be accessed.
2. When CSIAE0 is changed from 1 to 0, the registers and bits mentioned in Note above
are asynchronously initialized. To set CSIAE0 = 1 again, be sure to re-set the initialized
registers.
3. When CSIAE0 is re-set to 1 after CSIAE0 is changed from 1 to 0, it is not guaranteed that
the value of the buffer RAM will be retained.
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CHAPTER 17 SERIAL INTERFACE CSIA0
After reset: 00H R/W
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CSIAE0 ATE0 ATM0
CSIAE0 Control of CSIA0 operation enable/disable
0 CSIA0 operation disabled (SOA0: Low level, SCKA0: High level) and
asynchronously resets the internal circuit
1
CSIA0 operation enabled
ATE0 Control of automatic communication operation enable/disable
0 1-byte communication mode
1 Automatic communication mode
ATM0 Automatic communication mode specification
0
Single transfer mode (stops at the address specified by the ADTP0 register)
1
Repeat transfer mode (after transfer is complete, clear the ADTC0 register to 00H to resume transfer)
MASTER0
CSIA0 master/slave mode specification
0
Slave mode (synchronous with SCKA0 input clock)
1
Master mode (synchronous with internal clock)
Control of transmit operation enable/disable
TXEA0
Transmit operation disabled (SOA0: Low level)
0
1 Transmit operation enabled
Control of receive operation enable/disable
RXEA0
0 Receive operation disabled
Receive operation enabled
1
DIR0
0 MSB
1 LSB
User's Manual U15947EJ2V0UD
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MASTER0 TXEA0 RXEA0
Note
.
*
First bit specification
DIR0 0