Format Of Serial Status Register 0 (Csis0) - NEC 78K0 User Manual

(2) Serial status register 0 (CSIS0)
This is an 8-bit register used to control the communication operation and indicate status of CSIA0.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H. However, rewriting CSIS0 is prohibited when bit 0 (TSF0) is 1.
Figure 17-4. Format of Serial Status Register 0 (CSIS0) (1/2)
Address: FF91H After reset: 00H
Symbol 7
CSIS0
0
Notes 2, 3
STBE0
0
Strobe output disabled
1 Strobe output enabled
BUSYE0
0
Busy signal detection disabled (input via BUSY0 pin is ignored)
1
Busy signal detection enabled and communication wait by busy signal is executed
Note 4
BUSYLV0
0
Low level
1
High level
Notes 1. Bits 0 and 1 are read-only.
2. STBE0 is valid only in master mode.
3. When STBE0 is set to 1, two transfer clocks are consumed between byte transfers regardless of the
setting of automatic data transfer interval specification register 0 (ADTI0). That is, 10 transfer clocks
are used for 1-byte transfer if ADTI0 = 00H is set.
4. In bit error detection by busy input, the active level specified by BUSYLV0 is detected.
Caution Be sure to clear bits 6 and 7 to 0.
CHAPTER 17 SERIAL INTERFACE CSIA0
Note 1
R/W
6 5 4
0 STBE0 BUSYE0
Strobe output enable/disable
Busy signal detection enable/disable
Busy signal active level setting
*
User's Manual U15947EJ2V0UD
3 2
BUSYLV0 ERRE0
1 0
ERRF0 TSF0
383