Timing Of A/D Converter Sampling And A/D Conversion Start Delay - NEC 78K0 User Manual

(11) A/D converter sampling time and A/D conversion start delay time
The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM).
The delay time exists until actual sampling is started after A/D converter operation is enabled.
When using a set in which the A/D conversion time must be strictly observed, care is required for the contents
shown in Figure 13-21 and Table 13-3.
Figure 13-21. Timing of A/D Converter Sampling and A/D Conversion Start Delay
ADCS ← 1 or ADS rewrite
ADCS
Sampling timing
INTAD
Table 13-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value)
FR2 FR1 FR0
0 0 0
0 0 1
0 1 0
1 0 0
1 0 1
1 1 0
Other than above
Note The A/D conversion start delay time is the time after wait period. For the wait function, see CHAPTER 35
CAUTIONS FOR WAIT.
Remark f : X1 clock oscillation frequency
X
(12) Register generating wait cycle
Do not read data from the ADCR register and do not write data to the ADM, ADS, PFM, and PFT registers while
the CPU is operating on the subsystem clock and while oscillation of the clock input to X1 is stopped.
CHAPTER 13 A/D CONVERTER
Wait A/D Sampling
period conversion time
start delay
time
Conversion Time
288/f
X
240/f
X
192/f
X
144/f
X
120/f
X
96/f
X
Setting prohibited
User's Manual U15947EJ2V0UD
Conversion time
*
Sampling Time
40/f
X
32/f
X
24/f
X
20/f
X
16/f
X
12/f
X
−
Sampling
time
Conversion time
A/D Conversion Start Delay Time
MIN. MAX.
32/f 36/f
X X
28/f 32/f
X X
24/f 28/f
X X
16/f 18/f
X X
14/f 16/f
X X
12/f 14/f
X X
− −
Note
297