NEC 78K0 User Manual page 247

(e) Operation by changing CMP1n (CMP1n = 01H → 03H, CMP0n = A5H)
Count clock
8-bit timer counter Hn 00H 01H 02H
CMP0n
CMP1n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
<1>
<1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count
clock to count up. At this time, the TOHn output remains inactive (when TOLEVn = 0).
<2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous
to the count clock.
<3> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn
is cleared, the TOHn output becomes active, and the INTTMHn signal is output.
<4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the
values of 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to
the CMP1n register and the CMP1n register value is changed (<2>').
However, three count clocks or more are required from when the CMP1n register value is changed to when
the value is transferred to the register. If a match signal is generated within three count clocks, the changed
value cannot be transferred to the register.
<5> When the values of 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn output
becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
<6> Clearing the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive.
Remark n = 0, 1
CHAPTER 9 8-BIT TIMERS H0 AND H1
Figure 9-12. Operation Timing in PWM Output Mode (4/4)
A5H 00H 01H 02H 03H
01H 01H (03H)
<2>
<3>
*
User's Manual U15947EJ2V0UD
A5H 00H 01H 02H 03H
A5H
03H
<2>'
<4>
A5H 00H
<6>
<5>
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