NEC 78K0 User Manual page 157

(2) When "Ring-OSC can be stopped by software" is selected by mask option
Status 6
CPU clock: f
XT
f : Oscillation
XP
stopped
f : Oscillating/
R
oscillation
stopped
MCC = 0
MCC = 1
Status 5
CPU clock: f
XT
f : Oscillating
XP
f : Oscillating/
R
oscillation
stopped
Note 5
CSS = 0
Note 5
CSS = 1
Status 4
CPU clock: f
f : Oscillating
XP
f : Oscillation
R
stopped
Notes 1. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
2. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
3. When shifting from status 2 to status 1, make sure that MCS is 0.
4. When "Ring-OSC can be stopped by software" is selected by a mask option, the clock supply to the
watchdog timer is stopped after the HALT or STOP instruction has been executed, regardless of the
setting of bit 0 (RSTOP) of the Ring-OSC mode register (RCM) and bit 0 (MCM0) of the main clock
mode register (MCM).
5. The operation cannot be shifted between subsystem clock operation and Ring-OSC operation.
6. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
CHAPTER 6 CLOCK GENERATOR
Figure 6-13. Status Transition Diagram (2/4)
(when subsystem clock is used)
Interrupt
HALT
instruction
Interrupt
HALT
Interrupt
instruction
Status 3
RSTOP = 0
XP
CPU clock: f
f : Oscillating
XP
Note 1
RSTOP = 1
f : Oscillating
R
STOP
instruction
*
User's Manual U15947EJ2V0UD
Note 4
HALT
HALT
HALT
instruction
Interrupt
instruction
Status 2
MCM0 = 0
CPU clock: f
XP
f : Oscillating
XP
Note 2
MCM0 = 1
f : Oscillating
R
STOP
instruction
Interrupt
Interrupt
Note 4
STOP
HALT
instruction
Interrupt
Status 1
Note 3
MSTOP = 1
CPU clock: f
R
f : Oscillation
XP
stopped
MSTOP = 0
f : Oscillating
R
STOP
instruction
Interrupt
Reset release
Note 6
Reset
R
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