Chapter 26 Regulator; Outline Of Regulator; Block Diagram Of Regulator Periphery - NEC 78K0 User Manual

26.1 Outline of Regulator

The 78K0/KF1 includes a circuit to realize constant-voltage operation inside the device. To stabilize the regulator
output voltage, connect the REGC pin to V
regulator is 3.5 V (TYP.).
The supply voltage and oscillation frequency at which the regulator can be used are as follows.
• Power supply voltage: V
• Oscillation frequency: f
The regulator of the 78K0/KF1 stops operating in the following cases.
• During the reset period
• In STOP mode
• In HALT mode when the CPU is operating on the subsystem clock and when X1 oscillation is stopped
Figure 26-1 shows the block diagram of the periphery of the regulator.
Bidirectional
level shifter
Cautions 1. Directly connect the REGC pin of standard products and (A) grade products to V
regulator is not used.
2. The regulator cannot be used with (A1) and (A2) grade products. Be sure to connect the
REGC pin of these products directly to V
492

CHAPTER 26 REGULATOR

via a capacitor (1
SS
= 4.0 to 5.5 V
DD
= 2.0 to 8.38 MHz
X
Figure 26-1. Block Diagram of Regulator Periphery
EV system I/O buffer
DD
Internal digital circuits
A/D converter
X1, Ring,
sub
oscillator
AV
REF REGC
User's Manual U15947EJ2V0UD
µ
F: recommended). The output voltage of the
*
Flash memory
µ
( PD78F0148 only)
Regulator
V V
DD PP
µ
1 F
.
DD
EV
DD
when the
DD