Format Of 16-Bit Timer Capture/Compare Register 01N (Cr01N) - NEC 78K0 User Manual

(3) 16-bit timer capture/compare register 01n (CR01n)
CR01n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is
used as a capture register or a compare register is set by bit 2 (CRC0n2) of capture/compare control register 0n
(CRC0n).
CR01n can be set by a 16-bit memory manipulation instruction.
RESET input clears this register to 0000H.
Figure 7-5. Format of 16-Bit Timer Capture/Compare Register 01n (CR01n)
Address: FF14H, FF15H (CR010), FFB4H, FFB5H (CR011)
Symbol
CR01n
(n = 0, 1)
• When CR01n is used as a compare register
The value set in the CR01n is constantly compared with 16-bit timer counter 0n (TM0n) count value, and an
interrupt request (INTTM01n) is generated if they match. The set value is held until CR01n is rewritten.
• When CR01n is used as a capture register
It is possible to select the valid edge of the TI00n pin as the capture trigger. The TI00n valid edge is set by
prescaler mode register 0n (PRM0n) (see Table 7-3).
Table 7-3. CR01n Capture Trigger and Valid Edge of TI00n Pin (CRC0n2 = 1)
CR01n Capture Trigger
Falling edge
Rising edge
Both rising and falling edges
Remarks 1. Setting ES0n1, ES0n0 = 1, 0 is prohibited.
2. ES0n1, ES0n0: Bits 5 and 4 of prescaler mode register 0n (PRM0n)
CRC0n2:
µ
3. n = 0: PD780143, 780144
µ
n = 0, 1: PD780146, 780148, 78F0148
Cautions 1. If the CR01n register is cleared to 0000H, an interrupt request (INTTM01n) is generated after
the TM0n register overflows, after the timer is cleared and started on a match between the
TM0n register and the CR00n register, or after the timer is cleared by the valid edge of TI00n
or a one-shot trigger.
2. When CR01n is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
3. CR01n can be rewritten during TM0n operation. For details, see Caution 2 in Figure 7-20.
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
FF15H (CR010)
FFB5H (CR011)
*
Falling edge
Rising edge
Both rising and falling edges
Bit 2 of capture/compare control register 0n (CRC0n)
User's Manual U15947EJ2V0UD
After reset: 0000H R/W
FF14H (CR010)
FFB4H (CR011)
TI00n Pin Valid Edge
ES0n1
0
0
1
ES0n0
0
1
1
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