Timing Of Low-Voltage Detector Internal Reset Signal Generation - NEC 78K0 User Manual

Figure 25-4. Timing of Low-Voltage Detector Internal Reset Signal Generation
Supply voltage (V )
DD
LVI detection voltage
(V )
LVI
POC detection voltage
(V )
POC
2.7 V
<2>
LVIMK flag
(set by software)
LVIE flag
(set by software)
LVION flag
(set by software)
LVIF flag
LVIMD flag
(set by software)
Note 3
LVIRF flag
LVI reset signal
POC reset signal
Internal reset signal
Notes 1. The LVIMK flag is set to "1" by RESET input.
2. The LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 22
RESET FUNCTION.
Remark <1> to <8> in Figure 25-4 above correspond to <1> to <8> in the description of "when starting operation"
in 25.4 (1) When used as reset.
CHAPTER 25 LOW-VOLTAGE DETECTOR
Note 1
<1>
Not cleared
<3>
<4> 2 ms or longer
Not cleared
<5>
<6> 0.2 ms or longer
<7>
Note 2
Not cleared
<8>
*
Cleared by
software
User's Manual U15947EJ2V0UD
Not cleared
Not cleared
Not cleared
Cleared by
software
Time
Clear
Clear
Clear
Clear
485