Cautions For Watch Timer - NEC 78K0 User Manual

8-bit single-chip microcontrollers
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10.5 Cautions for Watch Timer

When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control register (WTM) (by
setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first interrupt request (INTWT) is generated
after the register is set does not exactly match the specification made with bit 3 (WTM3) of WTM. This is because
there is a delay of one 11-bit prescaler output cycle until the 5-bit counter starts counting. Subsequently, however, the
INTWT signal is generated at the specified intervals.
Figure 10-4. Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 s)
It takes 0.515625 seconds for the first INTWT to be generated (2
generated every 0.5 seconds.
WTM0, WTM1
INTWT
CHAPTER 10 WATCH TIMER
9
× 1/32768 = 0.015625 s longer). INTWT is then
0.515625 s
0.5 s
*
User's Manual U15947EJ2V0UD
0.5 s
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