NEC 78K0 User Manual page 624

Edition
2nd edition Deletion of input switch control register (ISC) from and addition of port registers (P0 to P7,
P12 to P14) to 4.3 Registers Controlling Port Function
Modification of setting of output latch of P40 to P47, P50 to P57, P64, P65, and P67 in
and addition of Note 2 to Table 4-5 Settings of Port Mode Register and Output Latch
When Using Alternate Function
Partial modification of descriptions in 4.4.1 (1) Output mode, 4.4.3 (1) Output mode,
and (2) Input mode
Addition of Caution to 5.1 External Bus Interface
Addition of Note to Figure 5-2 Format of Memory Expansion Mode Register (MEM)
Addition of Caution 2 to Figure 5-4 Format of Memory Expansion Wait Setting
Register (MM)
Addition of Remark to Figure 5-8 External Memory Read Modify Write Timing
Modification of Figure 6-1 Block Diagram of Clock Generator
Addition of Note to 6.3 (1) Processor clock control register (PCC)
Addition of Cautions 2 and 3 to Figure 6-6 Format of Oscillation Stabilization Time
Counter Status Register (OSTC)
Modification of Figure 6-8 Examples of External Circuit of X1 Oscillator, Figure 6-9
Examples of External Circuit of Subsystem Clock Oscillator, and Figure 6-10
Examples of Incorrect Resonator Connection
Modification of Notes 4 and 5 in Figure 6-13 Status Transition Diagram (2)
Modification of Note 4 and illustration in Figure 6-13 Status Transition Diagram (4)
Modification of Table 6-3 Relationship Between Operation Clocks in Each Operation
Status
Modification of Note in Figure 6-14 Switching from Ring-OSC Clock to X1 Input
Clock (Flowchart)
Addition of Note to Figure 6-16 Switching from X1 Input Clock to Subsystem Clock
(Flowchart)
Revision of CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Revision of CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Revision of CHAPTER 9 8-BIT TIMERS H0 AND H1
Modification of Figure 10-1 Watch Timer Block Diagram
Addition of Figure 10-4 Example of Generation of Watch Timer Interrupt Request
(INTWT) (When Interrupt Period = 0.5 s)
Modification of Figure 12-1 Block Diagram of Clock Output/Buzzer Output Controller
Revision of CHAPTER 13 A/D CONVERTER
Revision of CHAPTER 14 SERIAL INTERFACE UART0
624
APPENDIX D REVISION HISTORY
Description
*
User's Manual U15947EJ2V0UD
(3/5)
Applied to:
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5
EXTERNAL BUS
INTERFACE
CHAPTER 6 CLOCK
GENERATOR
CHAPTER 7 16-BIT
TIMER/EVENT
COUNTERS 00 AND 01
CHAPTER 8 8-BIT
TIMER/EVENT
COUNTERS 50 AND 51
CHAPTER 9 8-BIT
TIMERS H0 AND H1
CHAPTER 10 WATCH
TIMER
CHAPTER 12 CLOCK
OUTPUT/BUZZER
OUTPUT
CONTROLLER
CHAPTER 13 A/D
CONVERTER
CHAPTER 14 SERIAL
INTERFACE UART0