NEC 78K0 User Manual page 464

Ring-OSC clock
X1 input clock
Normal
CPU clock
operation
RESET
Internal
reset signal
Port pin
Note The port pins become high impedance, except for P130, which is set to low-level output.
Remark For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 24 POWER-
ON-CLEAR CIRCUIT and CHAPTER 25 LOW-VOLTAGE DETECTOR.
464
CHAPTER 22 RESET FUNCTION
Figure 22-4. Timing of Reset in STOP Mode by RESET Input
STOP instruction execution
Stop status
(Oscillation stop)
Delay
User's Manual U15947EJ2V0UD
Operation stop
Reset period
(17/f )
(Oscillation stop) R
Delay
Hi-Z
*
Normal operation
(Reset processing, Ring-OSC clock)
Note