NEC 78K0 User Manual page 304

Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2)
PS01
0
0
1
1
CL0
0
1
SL0
0
1
Note If "reception as 0 parity" is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial
interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur.
Cautions 1. At startup, set POWER0 to 1 and then set TXE0 to 1. To stop the operation, clear TXE0 to 0,
and then clear POWER0 to 0.
2. At startup, set POWER0 to 1 and then set RXE0 to 1. To stop the operation, clear RXE0 to 0,
and then clear POWER0 to 0.
3. Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0 pin. If
POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception is started.
4. TXE0 and RXE0 are synchronized by the base clock (f
transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks of base clock after
TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set within two clocks of base clock,
the transmission circuit or reception circuit may not be initialized.
5. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.
6. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with
"number of stop bits = 1", and therefore, is not affected by the set value of the SL0 bit.
7. Be sure to set bit 0 to 1.
304
CHAPTER 14 SERIAL INTERFACE UART0
PS00 Transmission operation
0 Does not output parity bit.
1 Outputs 0 parity.
0 Outputs odd parity.
1 Outputs even parity.
Specifies character length of transmit/receive data
Character length of data = 7 bits
Character length of data = 8 bits
Specifies number of stop bits of transmit data
Number of stop bits = 1
Number of stop bits = 2
User's Manual U15947EJ2V0UD
Reception operation
Reception without parity
Reception as 0 parity
Judges as odd parity.
Judges as even parity.
*
) set by BRGC0.
XCLK0
Note
To enable