NEC 78K0 User Manual page 27

Figure No.
18-1 Block Diagram of Multiplier/Divider......................................................................................................... 419
18-2 Format of Remainder Data Register 0 (SDR0) ....................................................................................... 420
18-3 Format of Multiplication/Division Data Register A0 (MDA0H, MDA0L) ................................................... 421
18-4 Format of Multiplication/Division Data Register B0 (MDB0).................................................................... 422
18-5 Format of Multiplier/Divider Control Register 0 (DMUC0) ....................................................................... 423
Timing Chart of Multiplication Operation (00DAH × 0093H) ................................................................... 425
18-6
Timing Chart of Division Operation (DCBA2586H ÷ 0018H)................................................................... 427
18-7
19-1 Basic Configuration of Interrupt Function ............................................................................................... 431
19-2 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H) .................................................... 434
19-3 Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H) ................................................ 435
19-4 Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H)......................................... 436
19-5 Format of External Interrupt Rising Edge Enable Register (EGP)
and External Interrupt Falling Edge Enable Register (EGN)................................................................... 437
19-6 Format of Program Status Word............................................................................................................. 438
19-7 Interrupt Request Acknowledgment Processing Algorithm ..................................................................... 440
19-8 Interrupt Request Acknowledgment Timing (Minimum Time) ................................................................. 441
19-9 Interrupt Request Acknowledgment Timing (Maximum Time) ................................................................ 441
19-10 Examples of Multiple Interrupt Servicing ................................................................................................ 443
19-11 Interrupt Request Hold ........................................................................................................................... 445
20-1 Block Diagram of Key Interrupt............................................................................................................... 446
20-2 Format of Key Return Mode Register (KRM).......................................................................................... 447
21-1 Format of Oscillation Stabilization Time Counter Status Register (OSTC) ............................................. 450
21-2 Format of Oscillation Stabilization Time Select Register (OSTS) ........................................................... 451
21-3 HALT Mode Release by Interrupt Request Generation .......................................................................... 454
21-4 HALT Mode Release by RESET Input.................................................................................................... 455
21-5 Operation Timing When STOP Mode Is Released ................................................................................. 458
21-6 STOP Mode Release by Interrupt Request Generation.......................................................................... 459
21-7 STOP Mode Release by RESET Input ................................................................................................... 460
22-1 Block Diagram of Reset Function ........................................................................................................... 462
22-2 Timing of Reset by RESET Input............................................................................................................ 463
22-3 Timing of Reset Due to Watchdog Timer Overflow................................................................................. 463
22-4 Timing of Reset in STOP Mode by RESET Input ................................................................................... 464
22-5 Format of Reset Control Flag Register (RESF) ...................................................................................... 468
23-1 Block Diagram of Clock Monitor ............................................................................................................. 469
23-2 Format of Clock Monitor Mode Register (CLM) ...................................................................................... 470
23-3 Timing of Clock Monitor .......................................................................................................................... 472
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User's Manual U15947EJ2V0UD
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