NEC 78K0 User Manual page 398

(2) Automatic transmit/receive data setting
(a) Transmit data setting
<1> Write transmit data from the least significant address FA00H of buffer RAM (up to FA1FH at
maximum). The transmit data should be in the order from lower address to higher address.
<2> Set the automatic data transfer address point specification register 0 (ADTP0) to the value obtained
by subtracting 1 from the number of transmit data bytes.
(b) Setting example of automatic transmission/reception mode
<1> Set bit 7 (CSIAE0) and bit 6 (ATE0) of serial operation mode specification register 0 (CSIMA0) to 1.
<2> Set bit 2 (RXEA0) and bit 3 (TXEA0) of CSIMA0 to 1.
<3> Set a data transfer interval in automatic data transfer interval specification register 0 (ADTI0).
<4> Set bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) to 1.
Caution Take relationship with the other party of communication when setting the port mode
register and port register.
The following operations are automatically carried out when (a) and (b) are carried out.
• After the buffer RAM data indicated by automatic data transfer address count register 0 (ADTC0) is
transferred to SIOA0, transmission is carried out (start of automatic transmission/reception).
• The received data is written to the buffer RAM address indicated by ADTC0.
• ADTC0 is incremented and the next data transmission/reception is carried out.
transmission/reception continues until the ADTC0 incremental output matches the set value of
automatic data transfer address point specification register 0 (ADTP0) (end of automatic
transmission/reception). However, if bit 5 (ATM0) of CSIMA0 is set to 1 (repeat mode), ADTC0 is
cleared after a match between ADTP0 and ADTC0, and then repeated transmission/reception is
started.
• When automatic transmission/reception is terminated, TSF0 is cleared to 0.
(3) Automatic transmission/reception communication operation
(a) Automatic transmission/reception mode
Automatic transmission/reception can be performed using buffer RAM.
The data stored in the buffer RAM is output from the SOA0 pin via the SIOA0 register in synchronization
with the SCKA0 falling edge by performing (a) and (b) in (2) Automatic transmit/receive data setting.
The data is then input from the SIA0 pin via the SIOA0 register in synchronization with the SCKA0 falling
edge and the receive data is stored in the buffer RAM in synchronization with the rising edge 1 clock
later.
Data transfer ends if bit 0 (TSF0) of serial status register 0 (CSIS0) is set to 1 when any of the following
conditions is met.
• Reset by clearing bit 7 (CSIAE0) of the CSIMA0 register to 0
• Transfer of 1 byte is complete by setting bit 1 (ATSTP0) of the CSIT0 register to 1
• Transfer of 1 byte is complete when bit 1 (ERRF0) of the CSIS0 register becomes 1 while bit 2
(ERRE0) = 1
• Transfer of the range specified by the ADTP0 register is complete
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CHAPTER 17 SERIAL INTERFACE CSIA0
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User's Manual U15947EJ2V0UD
Data