Multiplication/division data register B0
Remainder data register 0
(MDB0 (MDB0H+MDB0L)
(SDR0 (SDR0H+SDR0L)
Controller
17-bit
adder
Figure 18-1. Block Diagram of Multiplier/Divider
Internal bus
Multiplication/division data register A0
(MDA0H (MDA0HH + MDA0HL) + MDA0L (MDA0LH + MDA0LL))
Controller
*
Controller
Multiplier/divider control
register 0 (DMUC0)
DMUSEL0
DMUE
Start
MDA000
6-bit
counter
INTDMU
Clear
CPU clock