NEC 78K0 User Manual page 172

Table 7-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins
(1) TI00n pin valid edge selected as capture trigger (CRC0n1 = 1, CRC0n0 = 1)
CR00n Capture Trigger
Falling edge
Rising edge
No capture operation
(2) TI01n pin valid edge selected as capture trigger (CRC0n1 = 0, CRC0n0 = 1)
CR00n Capture Trigger
Falling edge
Rising edge
Both rising and falling edges
Remarks 1. Setting ES0n1, ES0n0 = 1, 0 and ES1n1, ES1n0 = 1, 0 is prohibited.
2. ES0n1, ES0n0:
ES1n1, ES1n0:
CRC0n1, CRC0n0: Bits 1 and 0 of capture/compare control register 0n (CRC0n)
µ
3. n = 0: PD780143, 780144
µ
n = 0, 1: PD780146, 780148, 78F0148
Cautions 1. Set a value other than 0000H in CR00n in the mode in which clear & start occurs on a match
of TM0n and CR00n. However, in the free-running mode and in the clear mode using the
valid edge of TI00n, if CR00n is cleared to 0000H, an interrupt request (INTTM00n) is
generated when the value of CR00n changes from 0000H to 0001H following overflow
(FFFFH).
2. When P01 or P06 is used as the valid edge input pin of TI01n, it cannot be used as the timer
output (TO0n). Moreover, when P01 or P06 is used as TO0n, it cannot be used as the valid
edge input pin of TI01n.
3. When CR00n is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
4. Do not rewrite CR00n during TM0n operation.
172
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
Rising edge
Falling edge
Both rising and falling edges
Falling edge
Rising edge
Both rising and falling edges
Bits 5 and 4 of prescaler mode register 0n (PRM0n)
Bits 7 and 6 of prescaler mode register 0n (PRM0n)
User's Manual U15947EJ2V0UD
TI00n Pin Valid Edge
TI01n Pin Valid Edge
*
ES0n1 ES0n0
0 1
0 0
1 1
ES1n1 ES1n0
0 0
0 1
1 1