Reception Completion Interrupt Request Timing - NEC 78K0 User Manual

(d) Reception
Reception is enabled and the R
interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1.
The 5-bit counter of the baud rate generator starts counting when the falling edge of the R
detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the
R D0 pin input is sampled again (
X
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift
register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion
interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an
overrun error (OVE0) occurs, however, the receive data is not written to RXB0.
Even if a parity error (PE0) occurs while reception is in progress, reception continues to the reception
position of the stop bit, and an error interrupt (INTSR0) is generated after completion of reception.
Figure 14-9. Reception Completion Interrupt Request Timing
Start
R D0 (input)
X
INTSR0
RXB0
Cautions 1. Be sure to read receive buffer register 0 (RXB0) even if a reception error occurs.
Otherwise, an overrun error will occur when the next data is received, and the reception
error status will persist.
2. Reception is always performed with the "number of stop bits = 1". The second stop bit
is ignored.
3. Be sure to read asynchronous serial interface reception error status register 0 (ASIS0)
before reading RXB0.
CHAPTER 14 SERIAL INTERFACE UART0
D0 pin input is sampled when bit 7 (POWER0) of asynchronous serial
X
in Figure 14-9). If the R
D0 D1 D2 D3 D4
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User's Manual U15947EJ2V0UD
D0 pin is low level at this time, it is recognized
X
D5 D6 D7 Parity
D0 pin input is
X
Stop
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