ASTB
WR
AD0 to AD7
A8 to A15
ASTB
WR
AD0 to AD7
A8 to A15
Internal wait signal
(1-clock wait)
ASTB
WR
AD0 to AD7
A8 to A15
WAIT
138
CHAPTER 5 EXTERNAL BUS INTERFACE
Figure 5-7. External Memory Write Timing
(a) No wait (PW1, PW0 = 0, 0) setting
Hi-Z
Lower address
Higher address
(b) Wait (PW1, PW0 = 0, 1) setting
Hi-Z
Lower
address
*
(c) External wait (PW1, PW0 = 1, 1) setting
Hi-Z
Lower
address
Higher address
User's Manual U15947EJ2V0UD
Write data
Write data
Higher address
Write data