Registers - IBM 3745 Maintenance Information Reference

The IN '77' bits are then set according to the logical rules:
IOC1 select = (IOC1 INT.) and ( LATCH = 1 or NO IOC2 INT.)
IOC2 select = (IOC2 INT.) and ( LATCH =0 or NO IOC1 INT.).
and the LATCH is then updated at IN '77' time according to the current IOC
selection.
LVL 1 Interrupt Reporting
1. IOC1 bus byte 0, bit 5 and IOC2 byte 0, bit 5 are ORed to produce a single
CA LVL 1 interrupt request.
2. IOC1 bus byte 1, bit 5 and IOC2 byte 1, bit 5 are ORed to produce a single
LA LVL 1 interrupt request. _
3. After interrupt recognition, the CCU executes an input X'7E' instruction to
identify the LVL 1 interrupt request origin. (See IN'7E' in this chapter.)
4. When the CCU executes the input X'76' instruction, the bit assignment of
byte 0 is for IOC1 and the bit assignment of byte 1 is for IOC2.
Cycle Steal Pointer Allocation
Each IOC bus may address up to eight channel adapters. The cycle steal
pointer registers are allocated as follows:
Adapter
IOC 1 IOC 2
Pointer type
CAs 30 - 37 60 - 67 Dedicated (NCP)
LAs 3F 6F Shared pointer
For IOC2, when a cycle steal is initiated, the ROS immediate field, X'6' (as
opposed to X'3' for IOC1), is concatenated to the value found in CSCW bits
11-14 (received from the adapter) to produce the pointer register address.
For all AIO operations, bit 5 (equal 0 for CA and 1 for LA) and bits 11-14 (pointer
number if bit 5 = 0 and scanner 10 if bit 5 = 1) of the CSCW are stored in an
external register accessible by the control program using input X'75'. (See
IN'75' in this chapter.)
Reset AIO, Stop AIO
Registers
General Registers
See: OUT X'76' and OUT X'79' in this chapter.
The controller has two types of register: general and external.
Forty general registers are available in the controller for program use. The
size of each register is 24 bits. The bits are assigned from left to right as byte
X, bits 0-7; byte 0, bits 0-7; and byte 1, bits 0-7.
The forty registers are divided into five groups of eight registers each. Each
group is assigned to a specific program level. Only one group of general regis-
ters is active at a given time (the group associated with the active program
2-24
IBM 3745 Maintenance Information Reference (MIR)